Circuit editing is a known process in which a modification is made to existing chip wiring to change the circuit functionality. Circuit editing may comprise, for example, breaking a connection between circuit portions (e.g., etching a gap into an existing wire), and creating a connection between circuit portions (e.g., depositing metal to form a new wire).
The circuit to be edited normally resides in a very small thickness of silicon at an upper side of a chip. However, because the upper side of the chip is covered with other features (e.g., C4 and BGA solder connections, etc.), the circuit to be edited is normally accessed through the backside of the chip. One conventional method includes removing a lid (e.g., heat spreader) from the backside of the chip, mechanically milling a substantial portion of the backside of the silicon die (e.g., backside thinning), and then forming a hole in the remaining silicon die over the portion of the circuit to be edited. At this point, the circuit is normally edited using a focused ion beam (FIB) process.
FIB is generally considered to be a sputtering process. Accelerated ions (e.g., gallium ions) of an ion beam strike a surface, knocking off material of the surface. Depending on what the beam hits, there is a certain yield (e.g., how many secondary particles are removed per primary beam ion). The yield is dependent on beam scan parameters, and is complicated by a competing phenomenon known as redeposition, in which some of the sputtered material lands on the sidewalls and re-attaches to the surface. In addition to circuit editing, FIB can also be used for milling (e.g., removing bulk material, such as silicon, etc.). However, FIB alone is unsatisfactory for milling since its mill rate quickly goes to zero in a deepening pit as redeposition equals sputtering.
Gas assisted etching (GAE) is a milling method in which FIB is used in conjunction with a reactive gas. In GAE processes, a small nozzle is placed above the chip surface and directs a small flow of a reactive gas (e.g., xenon difluoride (XeF2)) onto the surface to be milled (e.g., silicon, silicon dioxide, etc.). The atmosphere around the surface is held at a vacuum to remove constituents during the GAE process. Despite this vacuum, however, some of the flowing gas adsorbs to the surface a few monolayers thick. Energy, in the form of phonons (vibration) and secondary electrons from the ion beam striking the surface in the immediate vicinity, cracks the gas. In this beam driven decomposition reaction, the Xe is liberated, leaving a reactive specie of fluorine. The fluorine reacts with silicon products producing a volatile fluoride compound and clean removal of material via the vacuum. With little resulting redeposition, the process continues unimpeded, and can etch into the surface. GAE produces a beam directed etching, whereby a localized plasma/RIE-like etch process takes place substantially only where the beam is patterned (e.g., strikes the surface). Put another way, GAE produces an anisotropic etch (e.g., a vertical etch).
One disadvantage of GAE is that the reaction is limited by physics-based considerations. For example, too much ion beam energy will simply liberate the weakly bonded gas from the surface, resulting in reduced or no chemical reaction (e.g., reduced or no material removal). This is known as gas depletion mode, and more resembles a straight sputtering process. Accordingly, GAE processes are most typically used for small, precision mills of relatively small depth.
Bulk trenching (also referred to as high flow GAE) is a specialized form of GAE designed to clear large areas of backside silicon. Like GAE, bulk trenching is performed using reactive gas (e.g., XeF2) and a directed ion beam in the presence of a vacuum. Unlike GAE, bulk trenching utilizes higher partial pressures of reactive gas (e.g., XeF2) which results in silicon removal dominated more by a spontaneous contact reaction than by beam driven decomposition. The additional spontaneous component results in a semi-anisotropic etch (e.g., a substantially vertical etch).
The higher partial pressures utilized in bulk trenching are typically provided by employing a different type of nozzle to deliver the reactive gas. Such nozzles commonly have a large cylindrical opening at the tip, which the ion beam passes through. This allows the nozzle to be centered directly over the trench site, and helps to retain and concentrate the gas therein. Unfortunately, though, even the spontaneous reaction rate of bulk trenching is somewhat self limiting in that it slows down quickly as etching depth increases, which is why bulk trenching is considered as being semi-anisotropic.
In light of these conventional methods, standard practice for backside circuit editing involves mechanically thinning (e.g., grinding and polishing) the backside of the silicon chip (which typically starts at about 750 μm thick) down to around 100 μm thick or less, prior to placing the chip in the FIB. Subsequently, a bulk trenching process is applied to desired area(s) of the thinned chip to expose portions of the circuit for editing. One example of a bulk trenching process uses a beam current of around 20 nanoamps, an ion beam scan area of around 200 μm×200 μm, and the high flow nozzle for 25-30 minutes to mill through about 100 μm of silicon to the underside of the active devices.
A problem with this standard practice, however, is the high incidence of chip cracking. Most modern integrated circuits are C4 (e.g., controlled collapse chip connection) mounted on organic substrates to reduce cost. Mismatch of shrinkage and coefficients of thermal expansion (CTE) between the chip and the substrate causes large stresses to develop in the chip. For example, on large area chips, the CTE mismatch can cause the chip to camber (e.g., physically deflect from a planar configuration) by as much as 100 μm as the chip cools down to room temperature after the C4 solder attach process.
The aforementioned backside thinning process is typically performed using a milling machine and polishing process, and typically removes up to 675 μm of silicon from the backside of the chip (e.g., from a thickness of 775 μm to a thickness of 100 μm). However, due to the CTE induced stress in the chip, the chip often cracks during the backside thinning, which renders the chip unusable. As such, existing methods of mechanical milling prior to bulk trenching are expensive, time consuming, and generally incompatible with highly stressed silicon on organic substrates.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.